LTC2380-24 ADC sampling accuracy analysis report

The precision ADCs offered by Linear Technology provide a high level of performance. To achieve high performance, many design elements must be implemented correctly, such as low noise power supplies and references, proper bypassing, ground planes, fast setup drivers, and low jitter clocks. Even if one of the elements is not performing well, it will seriously affect the performance of the ADC.

The voltage applied to the ADC reference input is a particularly critical factor. Often in order to save money or board space, in a system with multiple precision ADCs, engineers will try to share a reference in the system without buffering each reference input. The reference pin in an ADC without an internal reference buffer is usually not a static node. When the ADC undergoes a conversion process, a series of spurs appear on the REF pin that must be processed quickly to allow the ADC to accurately convert the input signal. If the reference voltage is shared, these glitches can interfere with the conversion of adjacent ADCs. This happens even if the same type of ADC is converting at the same time. The purpose of this article is to illustrate what happens when multiple precision ADCs share a common reference to convince the reader to avoid this shortcut.

Figure 1. Two LTC2380-24 ADCs share a common reference

The circuit in Figure 1 shows that the two LTC2380-24 ADCs are connected in chain mode and have a common reference.

The LTC®2380-24 is a low noise, low power, high speed 24-bit successive approximation (SAR) ADC with integrated digital averaging filter. The LTC2380-24 has a dynamic range of 145dB with a sampling rate of 2Msps and a typical THD of -117dB. Place the 47μF reference bypass capacitor as close as possible to the REF pin of the ADC to maximize its performance. The data is taken through the circuit of Figure 1 and the circuit is modified by removing ADC A and grounding the RDL / SDI input of ADC B. For an ADC and two ADC cases, the timing is the same to minimize any differences in change time that may result.

Sampling Rate

As shown in Figure 2, sharing the reference voltage causes the THD to drop by 8dB at the maximum sample rate. When the sampling rate is slowed down to 125ksps, the difference drops to still a significant 4dB. A comparison of the THD and input amplitudes of Figure 3 shows that sharing a single reference voltage results in a THD drop of more than 10 dB compared to a single ADC, with input amplitudes ranging from -20 dBFS to -9 dBFS. THD performance is almost the same at input amplitudes below -30 dBFS. The biggest difference in performance is the comparison of THD and input frequency. Figure 4. At the input frequency of 41 kHz, two ADCs share a reference and THD performance begins to decrease. At an input frequency of 50 kHz, the THD performance of two ADCs sharing a single reference voltage is -49 dB difference, compared to -104 dB for a single ADC. Even at low input frequencies, the difference in THD is always greater than 7dB.

Figure 2. THD and sample rate for a common reference shared by one ADC and two ADCs

Figure 3. THD vs. input amplitude for an ADC and two ADCs sharing a common reference

Figure 4. THD and input frequency of an ADC and two ADCs sharing a common reference

The circuits and data provided are intended to demonstrate the performance penalty that occurs when multiple high performance ADCs share the same reference without the need for each reference input buffer. Significant THD degradation is demonstrated by sample rate, input amplitude and input frequency. After reading this information, anyone wishing to design a precision ADC circuit can be persuaded to use a separate reference voltage for each ADC used, or to buffer each ADC reference voltage input with a common reference voltage.

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