Detailed signal logic level standard
The logic level of the signal goes through the development of a single-ended signal to a differential signal, from a low-speed signal to a high-speed signal. The most basic single-ended signal logic level is CMOS, TTL. On this basis, as the voltage swing decreases, logic levels such as LVCMOS and LVTTL appear. As the signal rate increases, ECL, PECL, LVPECL, and LVDS appear. , CML and other differential signal logic levels.
1, signal logic level parameter concept definition logic level refers to the high and low level of the digital signal voltage, the relevant parameters are defined as follows:
(1) Input high-level threshold Vih: the minimum input high level allowed when the input of the logic gate is high. When the input level is higher than Vih, the input level is considered to be high level;
(2) Input low-level threshold Vil: the maximum input low level allowed when the input of the logic gate is low. When the input level is lower than Vil, the input level is considered to be low level;
(3) output high-level threshold Voh: the minimum value of the output level when the output of the logic gate is high, and the level value of the logic gate output must be greater than this Voh;
(4) Output low-level threshold Vol: the maximum value of the output level when the output of the logic gate is low, and the level of the logic gate when the output of the logic gate is low must be smaller than this Vol;
(5) Threshold level Vt: There is a threshold level in the digital circuit chip, which is the level at which the circuit has just barely flipped. It is a voltage value between Vil and Vih; for the threshold level of a CMOS circuit, it is basically one-half of the power supply voltage value, but to ensure a stable output, it is required to input a high level "Vih" , input low level "Vil. Tips: The threshold level is only used to characterize the digital circuit chip. The actual meaning of the actual hardware circuit design process is Vih and Vil. For general logic levels, the relationship between Vih, Vil, Voh, Vol, and Vt is: Voh "Vih" Vt "Vil" Vol
(6) Ioh: the load current when the logic gate output is high (to draw current);
(7) Iol: load current when the logic gate output is low (sink current);
(8) Iih: current when the logic gate input is high (sink current);
(9) Iil: Current when the logic gate input is low (current is drawn).
2. Common signal logic level parameters Commonly used logic levels are:
TTL, CMOS, ECL, PECL, LVDS, LVPECL, RS232, RS422, RS485, CML, SSTL, HSTL, etc.
(1) The logic levels of TTL and CMOS can be divided into four categories according to typical voltages:
5V series, 3.3V series, 2.5V series and 1.8V series, 3.3V TTL level and CMOS level are usually called LVTTL and LVCMOS;
(2) RS232/RS422/RS485 is the serial port (UART) level standard, RS232 is single-ended input and output, RS422 and RS485 are differential input and output;
(3) ECL, PECL, LVPECL, LVDS, CML are differential input and output levels;
(4) SSTL is mainly used for DDR memory, HSTL is mainly used for QDR memory; the standard standard parameters are as shown in the following table. The specific chip is recommended to refer to the Datasheet.
As can be seen from the above table, the commonly used differential signal level standards LVPECL, LVDS, CML have the same threshold parameters at the input and output. This is determined by the hardware structure that produces the differential signal.
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