Generally speaking, JTAG is roughly divided into two categories. One is used to test the electrical characteristics of the chip, and the chip is tested for problems. One type is used for Debug; the CPU is generally included in the CPU that supports JTAG.
A CPU with a JTAG Debug interface module can access the internal registers of the CPU and devices hung on the CPU bus through the JTAG interface, such as FLASH, RAM, SOC (such as 4510B, 44Box, AT91M series). Registers, registers like UART, TImers, GPIO, etc.
The above is only the capabilities of the JTAG interface. To use these functions, software coordination is required. The specific functions are determined by the specific software.
For example, download the program to the RAM function. Understand the SOC know that to use external RAM, you need to refer to the SOC DataSheet register description, set the RAM base address, bus width, access speed and so on. Some SOCs also require Remap to work properly. These settings are done by Firmware's initialization program when running Firmware. However, if the JTAG interface is used, the relevant registers may still be at the power-on value, or even the error value, the RAM does not work properly, so the download must fail. To use it normally, you must first find a way to set the RAM. In ADW, you can set it in the Console window with the Let command. In AXD, you can set it in the Console window with the Set command.
The following is a command sequence to set up the AT91M40800, turn off the interrupt, set CS0-CS3, and perform Remap, for AXD (ADS with Debug)
Setmem 0xfffff124, 0xFFFFFFFF, 32 --- close all interrupts
Setmem 0xffe00000,0x0100253d,32 ---Set CS0
Setmem 0xffe00004,0x02002021,32 ---Set CS1
Setmem 0xffe00008,0x0300253d,32 ---Set CS2
Setmem 0xffe0000C, 0x0400253d, 32 ---Set CS3
Setmem 0xffe00020,1,32 ---Remap
If you want to use it in ADW (DEBUG with SDT), you should change it to:
Let 0xfffff124=0xFFFFFFFF ---Close all interrupts
Let 0xffe00000=0x0100253d ---Set CS0
Let 0xffe00004=0x02002021 ---Set CS1
Let 0xffe00008=0x0300253d ---Set CS2
Let 0xffe0000C=0x0400253d ---Set CS3
Let 0xffe00020=1 ---Remap
For convenience, you can save the above command as a file config.ini, and enter ob config.ini in the Console window to execute.
Using other debugs is similar, except that the format of the commands and commands is different.
When setting the RAM, the set registers and the values ​​of the registers must match the settings of the program to be run. The target file generated by the general compilation is ELF format, or a similar format, including the target code running address, and the running address is determined at the time of Link. When the Debug downloader downloads the program, it downloads the program to the specified address according to the address information in the ELF file. If the base address of the RAM is set to 0x10000000, and the start address of the firmware is specified at 0x02000000 at compile time, the target code will be downloaded to 0x02000000 when downloading, obviously the download will fail.
All interrupts should be turned off before downloading the program via JTAG, which is the same reason that the firmware was turned off when the firmware was initialized. When using the JTAG interface, the enable of each interrupt is unknown, especially if there is an executable code in FLASH, and some interrupts may be enabled. After downloading the code using JTAG, when it is executed, it is possible that an interrupt is generated because the initialization is not completed, resulting in a program exception. Therefore, the interrupt needs to be turned off first, usually by setting the SOC interrupt control register.
Write Flash using JTAG. In theory, all devices on the CPU bus can be accessed through JTAG, so FLASH should be able to be written, but the FLASH write mode is very different from RAM, requires special commands, and different FLASH erases, programming commands are different, and blocks The size and quantity are different, and it is difficult to provide this feature. Therefore, Debug does not provide write Flash function, or only supports a small number of Flash.
As far as I know, for the arm, only the FlashPGM software provides the FLASH function, but it is also very troublesome to use. AXD, ADW do not provide write FLASH function. When I write the Flash method, I write a simple program, which is used to write the FLASH of the target board. I use the JTAG interface to download to the target board, and then load the target code to be written into the BIN format, and also to the target. The board (address and address of the program that burns FLASH is different), and then run the program that has been downloaded to burn FLASH. In this way, the speed seems to be faster than FlashPGM's write Flash.
About simple JTAG cable.
There are a variety of simple JTAG cables available, but they are just a level shifting circuit and also protect. JTAG logic is implemented by software running on a PC, so in theory, any simple JTAG cable can support a variety of applications, such as Debug. I used to write the Xilinx CPLD, AXD/ADW debugger using the same JTAG cable. The key is that with software support, most software does not provide a set function, so it can only support a certain JTAG cable.
About the speed of a simple JTAG cable.
JTAG is a serial interface, a simple JTAG cable using a print port, using the output of the print port with a latch feature, using software to generate JTAG timing through I / O. Determined by the JTAG standard, a series of operations are required to write/read a byte through JTAG. According to my analysis, using a simple JTAG cable, using the print port, and outputting a byte to the target board through JTAG, an average of 43 print ports are required. /O, On my machine (P4 1.7G), I can perform about 660K I/O operations per second, so the download speed is about 660K/43, which is about 15K Byte/S. For other machines, the I/O speed is roughly The same, generally in the 600K ~ 800K.
About how to improve JTAG download speed.
Obviously, using a simple JTAG cable does not increase speed. There are two ways to increase speed.
1. The JTAG interface is provided by the embedded system, and the embedded system and the microcomputer are connected by USB/Ethernet, which requires the use of the MCU.
2. Use CPLD/FPGA to provide JTAG interface, CPLD/FPGA and microcomputer use EPP interface (general computer print port supports EPP mode), EPP interface completes data transmission between microcomputer and CPLD/FPGA, CPLD/FPGA completes JTAG Timing.
These two methods have been implemented by myself. The first method can achieve a relatively high speed, the actual measurement exceeds 200KByte / S (note: it is Byte, not Bit); but relatively speaking, the hardware is complex and the manufacturing is relatively complicated. The second relatively speaking, the download speed is slower, reaching 96KByte/S at the fastest, but the circuit is simple, easy to manufacture, and the speed can meet the needs. The second solution also has a disadvantage. Since the CPU is not released when I/O operations are performed, the microcomputer CPU appears to be busy when downloading the program.
In general, I believe that the second method is preferable for individual lovers.
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